Integrated circuit chip designers continually integrate more and more features and functions into single integrated circuit chips. Integrating into such small scale often provides scale-related advantages and performance, which is why SoCs (system on chip) approaches have been of high interest in the past decade. However, very large chips with too many functions integrated on them often lead to a yield and thus cost disadvantage. Because the defect density of a semiconductor fabrication process is generally fixed per unit area, the chip yield often drops exponentially (not linearly) with an increase in area. One alternative to integrating all functions and features into a single large chip is to spread the functions and features out among multiple smaller chips, and package the chips together into a single integrated circuit package.
While conventionally employing multiple chips into a single package works well for its intended applications, there are often instances where the multiple chips need to communicate amongst themselves at very high data rates. Enabling such high-throughput communication among any two or more chips in the same package (or module) in a power efficient and cost efficient manner would be highly desirable.